Tuo Ma, Zhiwei Li, Qingjiang Li^*, Haijun Liu, Zhongjin Zhao, Yinan Wang

CMC-Computers, Materials & Continua, Vol.77, No.3, pp. 3237-3263, 2023, DOI:10.32604/cmc.2023.045948 - 26 December 2023

Abstract With the continuous development of deep learning, Deep Convolutional Neural Network (DCNN) has attracted wide attention in the industry due to its high accuracy in image classification. Compared with other DCNN hardware deployment platforms, Field Programmable Gate Array (FPGA) has the advantages of being programmable, low power consumption, parallelism, and low cost. However, the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator. The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing, but this method’s… More >

Marwa A. Elmenyawi^1,2,*, Radwa M. Tawfeek¹

Computer Systems Science and Engineering, Vol.46, No.2, pp. 1827-1844, 2023, DOI:10.32604/csse.2023.036474 - 09 February 2023

Abstract One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic… More >

M. Usharani^1,*, B. Sakthivel², S. Gayathri Priya³, T. Nagalakshmi⁴, J. Shirisha⁵

Computer Systems Science and Engineering, Vol.44, No.2, pp. 1647-1657, 2023, DOI:10.32604/csse.2023.027744 - 15 June 2022

Abstract Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for… More >

S. Rooban^1,*, A. Yamini Naga Ratnam¹, M. V. S. Ramprasad², N. Subbulakshmi³, R. Uma Mageswari⁴

CMC-Computers, Materials & Continua, Vol.73, No.3, pp. 5169-5184, 2022, DOI:10.32604/cmc.2022.027974 - 28 July 2022

Abstract Advanced technology used for arithmetic computing application, comprises greater number of approximate multipliers and approximate adders. Truncation and Rounding-based Scalable Approximate Multiplier (TRSAM) distinguish a variety of modes based on height (h) and truncation (t) as TRSAM (h, t) in the architecture. This TRSAM operation produces higher absolute error in Least Significant Bit (LSB) data shift unit. A new scalable approximate multiplier approach that uses truncation and rounding TRSAM (3, 7) is proposed to increase the multiplier accuracy. With the help of foremost one bit architecture, the proposed scalable approximate multiplier approach reduces the partial products. The proposed… More >

M. Maria Dominic Savio^1,*, T. Deepa¹, N. Bharathiraja², Anudeep Bonasu³

CMC-Computers, Materials & Continua, Vol.72, No.2, pp. 3815-3834, 2022, DOI:10.32604/cmc.2022.025924 - 29 March 2022

Abstract The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to… More >

Nagarajan Shanmugam^*, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Saravanakumar Natarajan

Computer Systems Science and Engineering, Vol.42, No.2, pp. 619-638, 2022, DOI:10.32604/csse.2022.021008 - 04 January 2022

Abstract In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the… More >

S. Sharmila Devi^1,*, V. Bhanumathi²

CMC-Computers, Materials & Continua, Vol.70, No.2, pp. 3609-3624, 2022, DOI:10.32604/cmc.2022.020426 - 27 September 2021

Abstract Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for… More >

Amr M. S. Mahdy^1,*, Mohamed S. Mohamed¹, Ahoud Y. Al Amiri², Khaled A. Gepreel¹

Intelligent Automation & Soft Computing, Vol.31, No.2, pp. 899-915, 2022, DOI:10.32604/iasc.2022.017801 - 22 September 2021

Abstract In this manuscript, we solve the ordinary model of nonlinear smoking mathematically by using the second kind of shifted Chebyshev polynomials. The stability of the equilibrium point is calculated. The schematic of the model illustrates our proposition. We discuss the optimal control of this model, and formularize the optimal control smoking work through the necessary optimality cases. A numerical technique for the simulation of the control problem is adopted. Moreover, a numerical method is presented, and its stability analysis discussed. Numerical simulation then demonstrates our idea. Optimal control for the model is further discussed by More >

Zihao Zong, Tielin Shi, Qi Xia^*

CMES-Computer Modeling in Engineering & Sciences, Vol.128, No.1, pp. 283-295, 2021, DOI:10.32604/cmes.2021.015975 - 28 June 2021

Abstract A parameter-free approach is proposed to determine the Lagrange multiplier for the constraint of material volume in the level set method. It is inspired by the procedure of determining the threshold of sensitivity number in the BESO method. It first computes the difference between the volume of current design and the upper bound of volume. Then, the Lagrange multiplier is regarded as the threshold of sensitivity number to remove the redundant material. Numerical examples proved that this approach is effective to constrain the volume. More importantly, there is no parameter in the proposed approach, which More >

Praveena R^{1, *}

CMC-Computers, Materials & Continua, Vol.63, No.1, pp. 85-95, 2020, DOI:10.32604/cmc.2020.08629 - 30 March 2020

Abstract Digital design of a digital signal processor involves accurate and high-speed mathematical computation units. DSP units are one of the most power consuming and memory occupying devices. Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices. This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit. A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier. Clock gating More >