Arpit Jain1,*, Adesh Kumar2, Anand Prakash Shukla3, Hammam Alshazly4, Hela Elmannai5, Abeer D. Algarni5, Roushan Kumar6, Jitendra Yadav6
Intelligent Automation & Soft Computing, Vol.34, No.3, pp. 2007-2021, 2022, DOI:10.32604/iasc.2022.024770
- 25 May 2022
Abstract Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D More >
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