Allam Abumwais*, Mahmoud Obaid
CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4951-4963, 2023, DOI:10.32604/cmc.2023.032822
- 28 December 2022
Abstract Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU)… More >
Login
Register
