Liangbo Xie1, *, Sheng Li1, Yan Ren1, Zhengwen Huang2
CMC-Computers, Materials & Continua, Vol.65, No.2, pp. 1519-1529, 2020, DOI:10.32604/cmc.2020.011701
- 20 August 2020
Abstract This paper presents a two-dimension time-domain comparator suitable for low
power successive-approximation register (SAR) analog-to-digital converters (ADCs). The
proposed two-dimension time-domain comparator consists of a ring oscillator collapsebased comparator and a counter. The propagation delay of a voltage controlled ring
oscillator depends on the input. Thus, the comparator can automatically change the
comparison time according to its input difference, which can adjust the power consumption
of the comparator dynamically without any control logic. And a counter is utilized to count
the cycle needed to finish a comparison when the input difference is small. Thus, the More >
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