Sheng Xiao1,*, Yong Chen2, Jing He3, Xi Yang4
Computer Systems Science and Engineering, Vol.46, No.3, pp. 3527-3540, 2023, DOI:10.32604/csse.2023.027081
- 03 April 2023
Abstract Read-write dependency is an important factor restricting software efficiency. Timing Speculative (TS) is a processing architecture aiming to improve energy efficiency of microprocessors. Timing error rate, influenced by the read-write dependency, bottlenecks the voltage down-scaling and so the energy efficiency of TS processors. We proposed a method called Read-Write Dependency Aware Register Allocation. It is based on the Read-Write Dependency aware Interference Graph (RWDIG) conception. Registers are reallocated to loosen the read-write dependencies, so resulting in a reduction of timing errors. The traditional no operation (Nop) padding method is also redesigned to increase the distance More >
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