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    ARTICLE

    A Universal BIST Approach for Virtex-Ultrascale Architecture

    N. Sathiabama1,*, S. Anila2

    Computer Systems Science and Engineering, Vol.45, No.3, pp. 2705-2720, 2023, DOI:10.32604/csse.2023.025941 - 21 December 2022

    Abstract Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test… More >

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