Open Access

ARTICLE

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

S. Senthilmurugan^1,*, K. Gunaseelan²

1 Department of Electronics and Communication Engineering, SRM Valliammai Engineering College, Chennai, 603203, India
2 Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai, 600025, India

* Corresponding Author: S. Senthilmurugan. Email:

Intelligent Automation & Soft Computing 2023, 35(2), 1323-1336. https://doi.org/10.32604/iasc.2023.027650

Received 22 January 2022; Accepted 01 March 2022; Issue published 19 July 2022

Abstract

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power density of the scaled multi-core architecture. Therefore, it losses reliability features to get overheating and increased temperature. This paper presents a novel power minimization technique for active 4-bit ALU operations using Fin Field Effect Transistor (FinFET) at 22 nm technology. Based on this, a diode is directly connected to the load transistor, and it is active only at the saturation region as a function. Thereby, the access transistor can cutoff of the leakage current, and sleep transistors control the flow of leakage current corresponding to each instant ALU operation. The combination of transistors (access and sleep) reduces the leakage current from micro to nano-ampere. Further, the power minimization is achieved by connecting the number of transistors (6T and 10T) of the FinFET structure to ALU with 22 nm technology. For simulation concerns, a Tanner (T-Spice) with 22 nm technology implements the proposed design, which reduces threshold voltage swing, supply power, leakage current, gate length delay, etc. As a result, it is quite suitable for the ALU architecture of a high-speed multi-core processor.

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