Open Access

ARTICLE

Optimized Power Factor Correction for High Speed Switched Reluctance Motor

R. S. Preethishri^*, J. Anitha Roseline, K. Murugesan, M. Senthil Kumaran

Sri Sivasubramaniya Nadar College of Engineering, Kalavakkam, Tamilnadu, 603110, India

* Corresponding Author: R. S. Preethishri. Email:

Intelligent Automation & Soft Computing 2023, 35(1), 997-1014. https://doi.org/10.32604/iasc.2023.025510

Received 26 November 2021; Accepted 12 February 2022; Issue published 06 June 2022

Abstract

The Power Factor Correction (PFC) in Switched Reluctance (SR) motor is discussed in this article. The SR motors are applicable for multiple applications like electric vehicles, wind mills, machineries etc. The doubly salient structure of SR motor causes the occurrence of torque ripples, which affects the power factor of the motor. To improve the power quality, the power factor has to be corrected and the ripples have to be minimized. In order to achieve these objectives, a novel power factor correction (PFC) method is proposed in this work. Here, the conventional Diode Bridge Rectifier (DBR) is replaced by a Bridgeless Hybrid Resonant (HR) converter, which assists in improvising the output in a wider range. The converter is chosen because of having variety of beneficial measures including high gain. The converter’s output is fed to the SR motor by means of an asymmetric Bridge Resonant (BR) converter. The proposed converter operates in continuous mode of conduction with the switching frequency of 10 KHz. A hysteresis current controller and Proportional Integral (PI) controller are utilized for reducing the harmonics in the source current along with the regulation of output voltage. In addition, the speed control of SR motor is accomplished by means of the Whale Optimization Algorithm (WOA) assisted PI controller. The proposed methodology is effective for the control of unity power factor, torque and current ripples. The Total Harmonic Distortion (THD) of the source current is also minimized, which suits the standard of International Electrotechnical Comission IEC 61000-3-2. By this methodology, the power factor of 0.99 is achieved with 97% efficiency and 3.92% THD. The proposed methodology is validated in simulation by MATLAB and in hardware by FPGA Spartan 6E.

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Keywords

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