Open Access

ARTICLE

Smart Communication Using 2D and 3D Mesh Network-on-Chip

Arpit Jain^1,*, Adesh Kumar², Anand Prakash Shukla³, Hammam Alshazly⁴, Hela Elmannai⁵, Abeer D. Algarni⁵, Roushan Kumar⁶, Jitendra Yadav⁶

1 Department of Computer Science, Teerthanker Mahaveer University, Moradabad, India
2 Department of Electrical & Electronics Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India
3 Government Polytechnic, Bijnor, 246276, Uttar Pradesh, India
4 Faculty of Computers and Information, South Valley University, Qena, 83523, Egypt
5 Department of Information Technology, College of Computer and Information Sciences, Princess Nourah bint Abdulrahman University, P.O.Box 84428, Riyadh 11671, Saudi Arabia
6 Department of Mechanical Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India

* Corresponding Author: Arpit Jain. Email:

Intelligent Automation & Soft Computing 2022, 34(3), 2007-2021. https://doi.org/10.32604/iasc.2022.024770

Received 30 October 2021; Accepted 12 January 2022; Issue published 25 May 2022

Abstract

Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication.

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Keywords

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