Open Access

ARTICLE

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

by P. Dhilipkumar^1,*, G. Mohanbabu²

1 Sri Ranganathar Institute of Engineering and Technology, Coimbatore, 641110, India
2 SSM Institute of Engineering and Technology, Dindigul, 624002, India

* Corresponding Author: P. Dhilipkumar. Email:

Intelligent Automation & Soft Computing 2022, 32(3), 1445-1458. https://doi.org/10.32604/iasc.2022.021663

Received 09 July 2021; Accepted 01 September 2021; Issue published 09 December 2021

Abstract

Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit’s enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

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Keywords

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