Open Access

ARTICLE

Performance Analysis of Low Power Interference Cancellation Architecture for OFDM System

N. Manikanda Devarajan^1,*, S. Thenmozhi², K. Jayaram³, R. Saravanakumar⁴

1 Department of Electronics and Communication Engineering, Malla Reddy Engineering College, Secunderabad, 500100, India
2 Department of Electronics and Communication Engineering, Dayanandasagar College of Engineering, Bangalore, 560078, India
3Department of Electronics and Communication Engineering, Erode Sengunthar Engineering College, Erode, 638057, India
4 Department of Wireless Communication, Institute of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha Institute of Medical and Technical Sciences, Chennai, India

* Corresponding Author: N. Manikanda Devarajan. Email:

Intelligent Automation & Soft Computing 2022, 32(2), 1167-1178. https://doi.org/10.32604/iasc.2022.021558

Received 06 July 2021; Accepted 07 August 2021; Issue published 17 November 2021

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) is a wireless communication technology that is used for highly reliable and high data rate communication. In a multi-user OFDM system, the interference has occurred in the receiver side between the consecutive OFDM symbols. This interference reduces the performance of the OFDM system. To achieve good quality in received symbols the interference level should be minimized. The conventional cancellation system requires higher interference reduction time and power. These limitations of the conventional interference cancellation architectures for OFDM systems are overcome by proposing efficient and low power interference cancellation architecture. Hence, this paper proposes a novel and efficient architecture based on logic gates for interference cancellation in multi-user OFDM systems. The proposed design consist of multiplexers, inverters and OR gate. The heuristic parameters for the proposed cancellation architecture are computed by performing an XOR operation. Compared to existing architecture, the proposed interference cancellation architecture consumes 7 mW of power consumption in the Virtex processor, 33.59 mW of power consumption in Spartan 3E processor and 0.029 mW of power consumption in the CPLD processor. This proposed interference cancellation architecture consumes fewer hardware resources and consumes low power. The proposed system is designed using Verilog High Definition Language (HDL) and synthesized in Xilinx Project Navigator 12.1i. Further, this paper also proposes gate diffusion input (GDI) based implementation of proposed interference cancellation architecture to analyse a delay and power consumption compared to other logic style implementation.

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Keywords

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