Open Access

ARTICLE

Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

G. Prathiba^1,*, M. Santhi²

1 Department of ECE, University College of Engineering, Ariyalur, 621705, India
2 Department of ECE, Saranathan College of Engineering, Trichy, 620012, India

* Corresponding Author: G. Prathiba. Email:

Intelligent Automation & Soft Computing 2022, 31(3), 1611-1626. https://doi.org/10.32604/iasc.2022.018975

Received 28 March 2021; Accepted 11 June 2021; Issue published 09 October 2021

Abstract

High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively.

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Keywords

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