A Novel Non-Isolated Cubic DC-DC Converter with High Voltage Gain for Renewable Energy Power Generation System

1  Introduction

The excessive utilization of conventional fossil fuels has been found to contribute significantly to the escalation of carbon emissions, thereby triggering a detrimental impact on the global environment, particularly through the exacerbation of global warming [1]. Moreover, due to the insufficient reserves of these traditional energy sources, the surging consumer demand remains unmet, necessitating the exploration of alternative avenues. Consequently, the pursuit of renewable energy sources has emerged as a paramount strategy to combat environmental pollution and address the ongoing energy crises, captivating the attention of researchers worldwide [2,3]. In order to facilitate the effective utilization of renewable energy, the development and implementation of renewable energy generation systems have become imperative. Nevertheless, the prevailing setback lies in the inability of current renewable energy generation systems to generate output voltage at levels sufficient to fulfill the requirements of the DC bus outputs [4,5]. This pressing challenge can be effectively surmounted through the application of DC-DC boost converter technology, as illustrated in Fig. 1. By employing the aforementioned DC-DC boost converter, the electricity derived from renewable energy sources can be effectively elevated to meet the voltage requirements of the DC bus, ensuring the smooth transmission of power to the load side. Consequently, the significance and demand for boost converters continue to experience an upward trajectory.

Figure 1: Typical application of DC-DC converter

Among the array of boost converters available, non-isolated DC-DC converters have garnered considerable interest owing to their relatively diminutive size, reduced losses, and cost-effectiveness [6]. With their uncomplicated structure and the ability to amplify voltage by adjusting the duty cycle, traditional non-isolated DC-DC converters have witnessed widespread adoption in industrial production settings [7]. The voltage gain ideally tends toward infinity as the duty cycle approaches unity. However, this amplified voltage gain can precipitate complications such as diode reverse recovery and transient response issues [8–10]. Additionally, the heightened current stress imposed on devices accentuates conduction losses, consequently impeding converter efficiency. Hence, while traditional DC-DC converters boast simplicity and affordability, their limited voltage boost ratio characteristics serve to restrict their range of application scenarios.

To achieve high voltage gain, researchers have conducted extensive investigations on high-gain DC-DC converters [11–14], such as quadratic DC-DC converters [15–17], two-switch DC-DC converters [18] and single-switch DC-DC converters [19–20]. For instance, references [21–23] proposed a cascade structure in the topology that enhances the overall output voltage by connecting two boost converters together in a back-to-back configuration. However, this particular topology necessitates the utilization of numerous components, engendering an enlargement in size, augmented costs, and increased power losses. References [24,25] introduced a quadratic DC-DC converter that exhibited high-voltage boost characteristics. Nonetheless, to attain a voltage gain of 10, this converter necessitates operation at an exceedingly high duty cycle, resulting in heightened device stress, which compromises the efficiency. The converter proposed in reference [26] attains an ultra-high voltage gain of 10 by operating at a duty cycle of 0.5. Alas, the associated topology manifests significant complexity, with the doubling unit alone comprising one inductor, three capacitors, and two diodes, resulting in a grand total of 18 components. As a consequence, this intricacy incurs elevated costs and power losses. Consequently, an only pursuit of voltage gains in DC-DC converters may inadvertently give rise to adverse implications such as escalated device stress and diminished conversion efficiency. Thus, for DC-DC boost converters, it is crucial to strike a balance among voltage gain, device stress, and power loss.

Switched-capacitor (SC) and switched-inductor (SL) technologies offer solutions to the above limitations. SC and SL possess the advantage of simple structures and low costs. The incorporation of SC and SL technology into a simple DC-DC boost converter holds the potential to optimize performance, enabling higher voltage gains while mitigating voltage stress on components. This approach facilitates the attainment of a harmonious balance between voltage gain, device stress, and power loss [12,20,27–30]. Furthermore, the amalgamation of SC and SL technology, leading to the emergence of switched inductor-capacitor (SL-SC) technology, presents an additional avenue to diminish voltage stress and power loss within DC-DC boost converters, attracting considerable attention in recent years [31–33]. Consequently, this paper proposes a novel cubic high-gain DC-DC boost converter that utilizes the incorporation of a SC unit and a SL-SC unit into the conventional quadratic DC-DC boost converter.

Section 2 provides a detailed description of the proposed converter, including its topology, operating mode, voltage gain, device stress, converter parameter design, and power loss. Section 3 presents an analysis that compares the converter in this paper with other converters. The simulation analysis results are presented in Section 4. Finally, Section 5 presents an experimental prototype that validates the theoretical analysis through experiments.

2  Details of the Proposed Converter

2.1 Configuration of the Proposed Converter

The topology of the proposed converter is illustrated in Fig. 2. This work suggests a novel non-isolated cubic DC-DC converter that incorporates a switched capacitor (SC) unit and a switched inductor-capacitor (SL-SC) unit into the traditional quadratic boost converter, resulting in a cubic boost ratio. SL-SC and SC may require more space due to the larger volume of inductors and capacitors. Additionally, fast charging and discharging in SL-SC and SC necessitate the use of high-speed switching devices, which may result in compromised performance and noise interference in high-frequency applications. Despite the aforementioned disadvantages of the converter, the advantages of the converter are significant, with the main benefits being:

Figure 2: A novel non-isolated cubic DC-DC converter

(1) The converter delivers high voltage gain while maintaining low device stress and high conversion efficiency.

(2) The cubic voltage gain of the converter results in an extensive input voltage range.

(3) Utilizing a single switch structure simplifies the control of the converter.

(4) The converter requires fewer components than the high-gain converters presented in references [22] and [26].

(5) The input current remains continuous, with shared ground facilities between the input and load terminals.

The converter comprises a switch (S), inductors (L1–L3), capacitors (C1–C4), diodes (D1–D6), and a resistance (R). Fig. 3 illustrates the switching characteristics of the proposed converter. The analysis of the operating principle of the proposed converter in the subsequent sections is based on the hypotheses: (1) the switch and diodes are considered ideal devices, (2) the capacitance is sufficiently large to maintain the capacitance voltage constant for one cycle, and (3) inductors L1, L2, and L3 all function in continuous conduction mode (CCM).

Figure 3: Switching characteristics of the converter: (a) Signals of reactive elements. (b) Signals of semiconductor elements

The converter features only one switch S, resulting in two operating modes within a single switching cycle TS, namely, conduction and off mode. Figs. 4 and 5 show the equivalent circuits of the two modes, with D representing the converter duty cycle. Detailed elaboration on the working principles of these modes will be provided in the subsequent sections.

Figure 4: Switch tube conduction mode of the proposed converter, 0 < t ≤ DTS

Figure 5: Switch tube off mode of the proposed converter, DTS<t ≤ TS

2.2 Switch Tube Conduction Mode

In the present mode (Fig. 4), the switch tube S is turned on, causing diodes D1, D4, and D6 to turn off by reverse voltage drop, while diodes D2, D3, and D5 turn on by forward voltage drop. The input voltage Vi transfers energy to the inductor L1; Capacitor C1 charges capacitor C2; The capacitor C1 charges the energy storage inductor L2; The capacitors C1 and C3 are connected in series to convey power to L3; The resistance R is powered by the capacitor C4. The waveform of inductive current iL1, iL2, and iL3 shows a linear upward trend. This process encompasses the following:

{L1diL1dt=Vi,L2diL2dt=VC1=VC2,L3diL3dt=VC1+VC3C1dVC1dt=−IL2−IC2−IL3,C2dVC2dt=IC2,C3dVC3dt=−IL3,C4dVC1dt=−Io(1)

2.3 Switch Tube off Mode

In switch tube off mode (Fig. 5), the switch tube S is turned off, D2, D3, and D5 are deactivated by withstanding a reverse voltage drop, and D1, D4, D6 are conducted by withstanding a forward voltage drop. The input voltage Vi and the input inductor L1 charge the capacitor C1; Vi, L1, C2, C3, L3 charge C4; L2 charges C3; The resistance R is powered by C4. The waveform of inductive current iL1, iL2, and iL3 shows a linear downward trend. This process includes:

{L1diL1dt=VC1−Vi;L2diL2dt=VC3;L3diL3dt=Vo−2VC1−VC3C1dVC1dt=IC2+IL1;C2dVC2dt=−IL3;C3dVC3dt=IL2−IL3;C4dVC1dt=IL3−Io(2)

2.4 Voltage Gain Equation

Based on the volt-second balance principle on the inductors within a single switching period TS, we can deduce that:

{DVi=(1−D)(VC1−Vi)DVC1=(1−D)VC3D(VC1+VC3)=(1−D)(Vo−2VC1−VC3)(3)

The voltage stress equations for capacitors C1~C4 can be obtained from Eq. (3):

{VC1=11−DViVC2=11−DViVC3=D(1−D)2ViVC4=Vo=1+(1−D)2(1−D)3Vi(4)

The mathematical expression for the voltage gain of the converter can be derived by using Eqs. (3)~(4):

M=VoVi=1+(1−D)2(1−D)3(5)

where Vi, Vo, M, and D are the input voltage, output voltage, voltage gain, and duty cycle of the converter, respectively. Therefore, the final output voltage of the proposed converter can be calculated using the subsequent expression:

Vo=1+(1−D)2(1−D)3Vi(6)

2.5 Calculation of Voltage Stress and Current Stress

In the conduction mode, the diodes D1, D4, and D6 are turned off; In the off mode, the diodes D2, D3, and D5 are turned off. The voltage across the switch tube S equals the voltage across the capacitor C4. The following formula is the voltage stress expression for switch tube S and diodes D1~D6:

{VS=VC4=Vo=1+(1−D)2(1−D)3ViVD1=VC1=11−DVi;VD2=11−DVi;VD3=1(1−D)3ViVD4=1(1−D)2Vi;VD5=D(1−D)3Vi;VD6=VC4=1+(1−D)2(1−D)3Vi(7)

According to the ampere-second balance principle on the capacitors, the current stress expressions for D1~D6 can be obtained:

{ID1=1(1−D)2Io;ID2=1D(1−D)2IoID3=(1+(1+D)2(1−D)3+1D)IoID4=11−DIo;ID5=D(1−D)2Io;ID6=Io(8)

The capacitive current stress can be obtained under the switch tube conduction and off mode:

{iC1={IoD(1−D)20≤t<DTsIo(1−D)2DTs≤t<Ts;iC2={IoD0≤t<DTs−Io1−DDTs≤t<TsiC3={−Io1−D0≤t<DTsDIo(1−D)2DTs≤t<Ts;iC4={−Io0≤t<DTsDIo1−DDTs≤t<Ts(9)

The mean current passing through the switch during the conduction mode is:

Ids=1−D(1−D)2(1−D)3Io(10)

2.6 Converter Parameter Design

Under lossless conditions, the input power and output power of the converter should be equivalent, so it can be expressed as:

{Pi=P0IiI0=V0Vi=M=1+(1−D)2(1−D)3Ii=IL1=(1+(1−D)2)(1−D)3IoIL1=(1+(1−D)2)2Vi(1−D)6R(11)

According to the ampere-second balance principle on C3 and C4, and combining Eqs. (1)~(2), it can be obtained that:

{D(−IL3)+(1−D)(IL2−IL3)=0D(−Io)+(1−D)(IL3−Io)=0(12)

The expressions of IL1~IL3 can be obtained from Eqs. (11)~(12):

{IL1=(1+(1−D)2)(1−D)3Io=(1+(1−D)2)2Vi(1−D)6RIL2=1(1−D)2Io=(1+(1−D)2)Vi(1−D)5RIL3=11−DIo=(1+(1−D)2)Vi(1−D)4R(13)

After turning on the switch tube, the voltages of the inductors L1~L3 can be obtained from Eq. (1), and we can derive the formula for the inductor current ripple as follows:

{L1diL1dt=Vi⇒ΔiL1DTs=ViL1⇒ΔiL1=ViDTsL1L2diL2dt=11−DVi⇒ΔiL2DTs=Vi(1−D)L2⇒ΔiL2=ViDTs(1−D)L2L3diL3dt=1(1−D)2Vi⇒ΔiL3DTs=Vi(1−D)2L3⇒ΔiL3=ViDTs(1−D)2L3(14)

According to the boundary conditions when the inductive current operates at CCM:

ILmin=IL−12ΔiL≥0(15)

By substituting Eqs. (13)~(14) into Eq. (15), the subsequent expression can be derived:

{(1+(1−D)2)2Vi(1−D)6R−ViDTs2L1≥0⇒L1≥(1−D)6DR2(1+(1−D)2)2fs(1+(1−D)2)Vi(1−D)5R−ViDTs2(1−D)L2≥0⇒L2≥(1−D)4DR2(1+(1−D)2)fs(1+(1−D)2)Vi(1−D)4R−ViDTs2(1−D)2L3≥0⇒L3≥(1−D)2DR2(1+(1−D)2)fs(16)

After activating the switch tube S, the current of the capacitors C1 to C4 can be obtained from Eq. (9), and the expression of the capacitor voltage ripple is obtained as follows:

{|C1dVC1dt|=|IoD(1−D)2|⇒|ΔVC1DTs|=|IoD(1−D)2C1|⇒ΔVC1=(1+(1−D)2)ViTsC1(1−D)5R|C2dVC2dt|=|IoD|⇒|ΔVC2DTs|=|IoDC2|⇒ΔVC2=(1+(1−D)2)ViTsC2(1−D)3R|C3dVC3dt|=|−Io1−D|⇒|ΔVC3DTs|=|−Io(1−D)C3|⇒ΔVC3=(1+(1−D)2)ViDTsC3(1−D)4R|C4dVC4dt|=|−Io|⇒|ΔVC4DTs|=|−Io|C4⇒ΔVC4=(1+(1−D)2)ViDTsC4(1−D)3R(17)

If the capacitance voltage ripple value does not exceed 1% of the average capacitance voltage, there are:

{ΔVC1≤1100VC1⇒ΔVC1≤1100×11−DVi⇒C1≥100×(1+(1−D)2)R(1−D)4fsΔVC2≤1100VC2⇒ΔVC2≤1100×11−DVi⇒C2≥100×(1+(1−D)2)R(1−D)2fsΔVC3≤1100VC3⇒ΔVC3≤1100×D(1−D)2Vi⇒C3≥100×(1+(1−D)2)R(1−D)2fsΔVC4≤1100VC4⇒ΔVC4≤1100×(1+(1−D)2)(1−D)3Vi⇒C4≥100×DRfs(18)

2.7 Power Loss Analysis

The converter’s power loss is composed of four primary components: capacitance loss, switch loss, diode loss, and inductance loss. Fig. 6 displays the equivalent circuit of the proposed converter, incorporating parasitic parameters, to investigate its power consumption. rs1 represents the parasitic resistance of the power switch, and ton and toff represent the conduction and off delay times of the switch, respectively. VF1~VF6 are the forward conduction voltage drops of diodes D1~D6, individually. rD1~rD6 are the forward conduction resistances of diodes D1~D6. rC1~rC4 represent the series parasitic resistance of capacitors C1~C4, respectively. rL1~rL3 represent the series parasitic resistance of inductors L1~L3, correspondingly.

Figure 6: Equivalent circuit of the converter considering parasitic parameters

When S is activated, the power loss produced by it is primarily categorized into conduction and switching losses. The total loss of the switch tube can be calculated using Eq. (19). Where Vds and Id are the average voltage and average current of the switch tube, IS_rms represents the effective value of the switch current.

PS_total=PS_conduction+PS_switching=(IS_rms)2rs+1Ts(∫0tonVds_avgIds_avgdt+∫0toffVdsidsdt)(19)

The power loss in diodes primarily results from forward conduction resistance and forward conduction voltage drop. The power loss of the diode can be calculated by Eq. (20). Where ID_ rms represents the effective value of diode current, ID_avg represents the average value of diode current.

PD_total=PD_rD+PD_VF=∑n=16(IDn_rms2rDn)+∑n=16(IDn_avgVFn)(20)

The inductance loss and capacitance loss are mainly generated by their respective series parasitic resistors. The calculation formula is shown as Eq. (21). Where IL_ rms and IC_ rms represent the effective value of the inductive current and the effective value of the capacitive current, respectively.

{PL_total=∑n=13ILn_rms2rLnPC_total=∑n=14ICn_rms2rCn(21)

The total power loss of the converter is:

PLoss=PS−total+PD−total+PC_total+PL_total(22)

The conversion efficiency of the converter can be obtained from Eq. (23), where Po represents the output power.

η=P0P0+PLoss×100%(23)

3  Comparison with Other Converters

The present study compares the voltage gain, switch voltage stress, and switch quantity of the proposed converter with other high-gain converters, as outlined in Table 1. For equitable comparison, this study selects the capacitor and the diode with the lowest stress values from each converter. The minimum voltage stress of the capacitor and diode for various converters is also presented in Table 1.

The findings indicate that the proposed converter offers decreased switch tube quantity and simpler control when compared to the references [17] and [27]. While the number of switching tubes in other references aligns with that in this study, there are variations in voltage gain and device stress. To provide a visual comparison, Figs. 7a~7d display the curve of voltage gain vs. duty ratio D (D = 0.2 to 0.7), the curve of diode stress vs. voltage gain, the curve of capacitor stress vs. voltage gain, and the curve of switch stress vs. voltage gain, respectively. Under the same duty ratio, the proposed converter has a larger gain value compared to converters [13–17,20,27], conventional quadratic boost converter and conventional cubic boost converter, as depicted in Fig. 7a. At a duty cycle of 0.4, the proposed converter achieves a voltage gain of 6.3, which is 1.73, 1.34, 3.57, 1.71, 1.56 and 1.17 times the voltage gain in references [13,14,16,17,20] and [27], respectively, and even 15.36 times the voltage gain in reference [15], reflecting the high gain advantage of the proposed converter. Furthermore, Figs. 7b and 7c suggest that the proposed converter provides the advantage of low voltage stress for the capacitor and diode. As depicted in Fig. 7d, the voltage stress on the power switch of the proposed converter is less than that in references [13,15–16], and is flush with traditional quadratic and traditional cubic boost converters. While the switch voltage stress in converters [14,17,20] and [27] is lower, these converters require higher duty ratios to obtain the desired voltage boost ratio. This can lead to transient response issues [19]. Additionally, the capacitor and diode stress in these converters is higher. Therefore, overall, when compared to other converters, the proposed converter offers significant advantages in terms of both device stress and voltage gain.

Figure 7: Comparison of converters: (a) voltage gain vs. duty ratio, (b) diode stress vs. voltage gain, (c) capacitor stress vs. voltage gain, (d) switch stress vs. voltage gain

4  Simulation Analysis

Table 2 lists the main circuit parameters for closed-loop simulation. The selection of inductor values L1, L2, and L3 considers the minimum inductance requirement specified in Eq. (16), while retaining a certain margin and taking into account cost and performance. Similarly, capacitor parameters C1, C2, C3, and C4 are chosen to meet the minimum capacitance value requirement stated in Eq. (18), while also retaining a certain margin and considering cost and performance.

The simulation waveforms of different devices with a duty ratio of 0.4 are presented in Fig. 8. Figs. 8a~8c indicate that the average currents of inductors L1, L2, and L3 are 4.71, 1.98, and 1.25 A, respectively, which are consistent with the results obtained from Eq. (13). Fig. 8a shows that the input current (equal to inductance L1 current) is essentially continuous, which is crucial for the application of new energy [20]. Additionally, the average output current is around 0.75 A, as shown in Fig. 8d, which confirms the theoretical analysis results. The capacitor voltage waveform is shown in Figs. 8e~8h, the average voltages of capacitors C1, C2, C3, and C4 are approximately 20, 20, 13.3, and 75.5 V, respectively, consistent with the theoretical analysis results obtained in Eq. (4). Figs. 8i~8p display the semiconductor voltage and output voltage waveforms. For the proposed converter, the load voltage is equal to the output voltage. According to Fig. 8j, the output voltage (load voltage) is around 75.5 V, which is achieved with an input voltage of 12 V. The voltage gain is 6.3. The simulation results verify the high-gain advantage of the proposed converter. Moreover, the voltage of the switch tube is about 75.5 V, as shown in Fig. 8i. The voltages of diodes D1, D2, D3, D4, D5, and D6 in Figs. 8k~8p are approximately 20, 20, 55.5, 33.3, 22.25, and 75.5 V, respectively, consistent with the theoretical calculation results in Eq. (7).

Figure 8: Simulation results: (a) current through the L1, (b) current through the L2, (c) current through the L3, (d) ouput current Io, (e) voltage across the C1, (f) voltage across the C2, (g) voltage across the C3, (h) voltage across the C4, (i) voltage across the S, (j) output voltage Vo (i.e., load voltage VR), (k) voltage of the D1, (l) voltage of the D2, (m) voltage of the D3, (n) voltage of the D4, (o) voltage of the D5, (p) voltage of the D6

In summary, the simulation analysis results confirm the validity of the theoretical analysis and demonstrate the excellent boost and device stress characteristics of the suggested converter.

The proposed converter employs the UC3842AN chip and peak current control (PCM) as its control strategy. Under this control strategy, dynamic simulation waveforms of the output voltage when input voltage jumps (Fig. 9a) are obtained, as shown in Fig. 9b. Additionally, dynamic simulation waveforms of the converter’s output voltage and output current during the transition from half to full load are acquired, as depicted in Figs. 9c and 9d, respectively. As demonstrated in Fig. 9b, when the input voltage changes in steps between 10 and 16 V, the output voltage undergoes dynamic responses. The overshoot of the output voltage is small, less than 0.8 V in both cases, and the adjustment time is short, less than 15 ms in both cases. Observations from Figs. 9c and 9d reveal that when output power jumps from half load, 28.5 W, to full load, 57 W, the output voltage experiences a small overshoot, approximately 1 V, while the adjustment time is approximately 16 ms. Subsequently, the output voltage stabilizes at around 75.5 V, and the output current stabilizes at around 0.75 A. These dynamic simulation results suggest that the proposed converter exhibits excellent dynamic performance.

Figure 9: The dynamic simulation waveforms: (a) input voltage with a step change; (b) output voltage dynamic response; (c) output voltage in the transition from 28.5 to 57 W; (d) output current in the transition from 28.5 to 57 W

5  Experimental Analysis

To further verify the accuracy and validity of the theoretical model, this study constructs an experimental prototype for testing. The prototype operates on an input voltage of 12 V, produces an output voltage of 75.5 V, and has a full load power of 57 W. Table 3 presents the key parameters of the experimental prototype. The values of capacitors and inductors in the experiment are consistent with the simulation, while also meeting the requirements of Eqs. (16) and (18), retaining a certain margin and considering performance and cost comprehensively. Then, device models are selected based on the values of capacitors and inductors. Fig. 10 showcases the physical appearance of the experimental prototype. Fig. 11 illustrates the experimental waveforms of the switch driving voltage VGS, power switch voltage VS, output voltage Vo (i.e., load voltage VR), capacitor C1 voltage VC1, diode D1 voltage VD1, diode D4 voltage VD4, inductor L1 current IL1, and output current Io at a duty cycle of 0.4.

Figure 10: The physical appearance of the experimental prototype

Figure 11: Experimental waveforms: (a) switching tube drive voltage VGS, (b) switching tube voltage VS, (c) output voltage Vo (i.e., load voltage VR), (d) capacitor C1 voltage VC1, (e) VD1 voltage across D1, (f) diode D4 voltage VD4, (g) inductor L1 current IL1, (h) output current Io

As depicted in Fig. 11a, the switch tube’s driving voltage VGS signal cycle is approximately 20 μs (frequency f = 50 kHz). The conduction drive voltage is 15 V, while the turn-off drive voltage is −5 V. The drive voltage signal meets the requirements of the SiC switch tube. Experimental results in Figs. 11b~11h are basically in agreement with theoretical calculation results. Nonetheless, the components are actually not ideal, and there are slight discrepancies between experimental and theoretical results. From Figs. 11c and 11h, the prototype’s output voltage Vo (i.e., load voltage) and output current Io are about 72.9 V and 0.72 A, respectively. However, the theoretical calculated values for Vo and Io are 75.5 V and 0.75 A, respectively. The experimental values for Vo and Io are lower by 3.44% and 4%, respectively, due to power loss of the devices. Fig. 11d illustrates that the capacitor voltage Vc1 is consistent with the theoretical value of 20 V. The capacitor voltage stress is relatively low. From Figs. 11e~11f, diode voltages VD1 and VD4 are approximately 19.8 and 32.2 V, respectively, consistent with theoretical calculation results. The experimental prototype has a higher voltage gain and lower device stress at a lower duty cycle. Table 4 presents a comprehensive comparison of the theoretical calculations, simulations, and experimental results for each parameter of the converter proposed in this paper. Table 4 indicates that the simulation and experimental results are largely consistent with the theoretical calculations, exhibiting minor errors, which affirms the accuracy of the theoretical analysis.

Fig. 12 illustrates the dynamic experimental waveform of the output voltage when the converter transitions from half load to full load. As indicated by Fig. 12, when the output power jumps from 28.5 to 57 W, the output voltage experiences a dynamic response, demonstrating a slight overshoot of approximately 2.1 V and a short adjustment time of approximately 18 ms. The experimental dynamic analysis results also attest to the proposed converter’s excellent dynamic performance.

Figure 12: Output voltage dynamic experimental waveform

The power loss and conversion efficiency of the converter proposed in this paper are further analyzed. The theoretical efficiency and experimental efficiency of the converter are compared under varying duty ratios, as illustrated in Fig. 13a. While the experimental efficiency is slightly lower than the theoretical efficiency, the two measures remain generally close, exhibiting an error of less than 3%. This validates the accuracy of the theoretical calculation. Moreover, as the duty cycle increases, the theoretical and experimental efficiencies first increase and then decrease. Notably, when the duty ratio is 0.4, the power loss is found to be the smallest, and the theoretical and experimental efficiencies are the highest, reaching 93% and 91.9%, respectively. This observation confirms that the converter proposed in this study boasts high voltage gain and low device stress, while also achieving high conversion efficiency.

Figure 13: Power loss, conversion efficiency, and comparison: (a) the theoretical conversion efficiency and experimental efficiency of the proposed converter, (b) the experimental efficiency comparison, (c) the power loss distribution of the proposed converter

Furthermore, a comparison is made between the experimental efficiency of the proposed converter and that of a converter presented in a prior study [34], both under the same input voltage of 12 V, as illustrated in Fig. 13b. Although the efficiency of the proposed converter is almost identical to that of the converter [34] at a duty ratio of 0.6, the proposed converter exhibits a higher efficiency than the latter at duty ratios of 0.2, 0.3, 0.4, and 0.5, thus presenting a notable conversion efficiency advantage. Finally, Fig. 13c illustrates the power loss distribution of the proposed converter at a duty ratio of 0.4. The switch tube loss is the smallest, accounting for only 1% of the total loss. Meanwhile, the capacitor, inductor, and diode losses are found to account for 1.5%, 2.3%, and 3.3%, respectively. To further enhance the efficiency of the converter proposed in this work, high-quality circuit devices could be utilized.

6  Conclusion

This study introduces a novel non-isolated cubic high-gain DC-DC converter based on the traditional quadratic DC-DC boost converter by incorporating a SC and a SL-SC unit. Firstly, the proposed converter’s details are elaborated, including its topology structure, operating mode, voltage gain, device stress, and power loss. Subsequently, a comparative analysis is conducted on the voltage gain and device stress between the proposed converter and other high-gain converters. Then, a closed-loop simulation system is constructed to obtain simulation waveforms of various devices and explore the dynamic performance. Lastly, an experimental prototype is built, experimental waveforms are obtained, and the experimental dynamic performance and conversion efficiency are analyzed. The theoretical analysis’s correctness is verified through simulation and experimental results. The proposed converter achieves a high voltage gain at low device stress and high conversion efficiency, realizing a good balance between voltage gain, device stress, and power loss. The proposed converter is well-suited for renewable energy systems and holds theoretical significance and practical value in renewable energy applications. It offers a viable solution to the issue of low output voltage in renewable energy power generation systems. In future research, the emphasis will be placed on verifying the practical application effect of the proposed converter in renewable energy systems, exploring its working performance in various renewable energy systems such as new energy vehicles and photovoltaic power generation, and targeting improvements and optimizations to enhance its practicality.

Acknowledgement: The authors express their gratitude to the editor and anonymous reviewers for their reviews and valuable comments.

Funding Statement: This work was supported by China Railway Corporation Science and Technology Research and Development Project (P2021J038).

Author Contributions: The authors confirm their contribution to the paper as follows: Qin Yao: Conceptualization, Methodology, Simulation, Experiment, Drawing, Data processing, Writing-original draft, Writing-review & editing; Yida Zeng: Communication, Resources; Qingui Jia: Experimental support.

Availability of Data and Materials: Data supporting this study are included within the article.

Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study.

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