Open Access

ARTICLE

Performance-Oriented Layout Synthesis for Quantum Computing

by Chi-Chou Kao^1,*, Hung-Yi Lin²

1 Department of Computer Science and Information Engineering, National University of Tainan, Tainan, 700301, Taiwan
2 Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung, 811, Taiwan

* Corresponding Author: Chi-Chou Kao. Email:

Computer Systems Science and Engineering 2024, 48(6), 1581-1594. https://doi.org/10.32604/csse.2024.055073

Received 15 June 2024; Accepted 31 July 2024; Issue published 22 November 2024

Abstract

Layout synthesis in quantum computing is crucial due to the physical constraints of quantum devices where quantum bits (qubits) can only interact effectively with their nearest neighbors. This constraint severely impacts the design and efficiency of quantum algorithms, as arranging qubits optimally can significantly reduce circuit depth and improve computational performance. To tackle the layout synthesis challenge, we propose an algorithm based on integer linear programming (ILP). ILP is well-suited for this problem as it can formulate the optimization objective of minimizing circuit depth while adhering to the nearest neighbor interaction constraint. The algorithm aims to generate layouts that maximize qubit connectivity within the given physical constraints of the quantum device. For experimental validation, we outline a clear and feasible setup using real quantum devices. This includes specifying the type and configuration of the quantum hardware used, such as the number of qubits, connectivity constraints, and any technological limitations. The proposed algorithm is implemented on these devices to demonstrate its effectiveness in producing depth-optimal quantum circuit layouts. By integrating these elements, our research aims to provide practical solutions to enhance the efficiency and scalability of quantum computing systems, paving the way for advancements in quantum algorithm design and implementation.

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