Open Access

ARTICLE

A Universal BIST Approach for Virtex-Ultrascale Architecture

by N. Sathiabama^1,*, S. Anila²

1 CSI College of Engineering, Ketti, 643215, Tamilnadu, India
2 Sri Ramakrishna Institute of Technology, Coimbatore, 641010, Tamilnadu, India

* Corresponding Author: N. Sathiabama. Email:

Computer Systems Science and Engineering 2023, 45(3), 2705-2720. https://doi.org/10.32604/csse.2023.025941

Received 10 December 2021; Accepted 14 June 2022; Issue published 21 December 2022

Abstract

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

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Keywords

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