Open Access

ARTICLE

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

Nagarajan Shanmugam^*, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Saravanakumar Natarajan

Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, 642003, Tamil Nadu, India

* Corresponding Author: Nagarajan Shanmugam. Email:

Computer Systems Science and Engineering 2022, 42(2), 619-638. https://doi.org/10.32604/csse.2022.021008

Received 18 June 2021; Accepted 18 September 2021; Issue published 04 January 2022

Abstract

In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more effective in the smallest n columns, and the accurate compressor in the remaining most significant columns. This limits the error in the multiplier output to be not more than 2ⁿ for an n X n multiplication. The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result. As an enhancement to the proposed multiplier, we introduce two Area Efficient (AE) variants viz., Proposed-AE (P-AE), and P-AE with Error Recovery (P-AEER). The proposed basic P-AE, and P-AEER designs exhibit 46.7%, 52.9%, and 52.7% PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology. The proposed design and their performance validation are done by using Cadence Encounter. The performance evaluations are carried out using cadence encounter with 90nm ASIC technology. The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%, 52.9% and 52.7% PDP reduction compared to the minimal error approximate multiplier. The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index (SSIM), to the least, and less than 3% deviation in ECG signal processing application.

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Keywords

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