Open Access

ARTICLE

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

by Jungyeon Lee¹, Malik Summair Asghar^1,2, HyungWon Kim^1,*

1 Department of Electronics, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, 28644, Korea
2 Department of Electrical and Computer Engineering, COMSATS University Islamabad, Abbottabad Campus, University Road, Tobe Camp, Abbottabad, 22044, Pakistan

* Corresponding Author: HyungWon Kim. Email:

Computers, Materials & Continua 2023, 75(2), 4357-4375. https://doi.org/10.32604/cmc.2023.031372

Received 15 April 2022; Accepted 30 January 2023; Issue published 31 March 2023

Abstract

As deep learning techniques such as Convolutional Neural Networks (CNNs) are widely adopted, the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip (SoC). Although conventional CNN accelerators can reduce the computational time of learning and inference tasks, they tend to occupy large chip areas due to many multiply-and-accumulate (MAC) operators when implemented in complex digital circuits, incurring excessive power consumption. To overcome these drawbacks, this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter (ADC). This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips. ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory. This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register (SAR) ADC. Unlink most other SAR-ADCs with differential structure; the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption. The SAR ADC implementation also introduces a unique circuit that reduces kick-back noise to increase performance. It was implemented in a test chip using a 55 nm CMOS process. It demonstrates that the proposed ADC reduces Kick-back noise by 40% and consequently improves the ADC’s resolution by about 10% while providing a near rail-to-rail dynamic range with significantly lower power consumption than conventional ADCs. The ADC test chip shows a chip size of 4600 μm² with a power consumption of 6.6 μW while providing an signal-to-noise-and-distortion ratio (SNDR) of 68.45 dB, corresponding to an effective number of bits (ENOB) of 11.07 bits.

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