Open Access

ARTICLE

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Mohanapriya Marimuthu¹, Santhosh Rajendran², Reshma Radhakrishnan², Kalpana Rengarajan³, Shahzada Khurram⁴, Shafiq Ahmad⁵, Abdelaty Edrees Sayed⁵, Muhammad Shafiq^6,*

1 Department of CSE, Coimbatore Institute of Technology, Coimbatore, 641014, India
2 Department of CSE, Karpagam Academy of Higher Education, Coimbatore, 641021, India
3 Department of Electronics and Communication Engineering, Veltech Multitech Dr. Rangarajan Dr. Sakunthala Engineering, Chennai, 600062, India
4 Faculty of Computing, The Islamia University of Bahawalpur, Bahawalpur, 63100, Pakistan
5 Industrial Engineering Department, College of Engineering, King Saud University, P.O. Box 800, Riyadh, 11421, Saudi Arabia
6 Department of Information and Communication Engineering, Yeungnam University, Gyeongsan, 38541, Korea

* Corresponding Author: Muhammad Shafiq. Email:

Computers, Materials & Continua 2023, 74(3), 4729-4745. https://doi.org/10.32604/cmc.2023.033020

Received 04 June 2022; Accepted 05 July 2022; Issue published 28 December 2022

Abstract

Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a field-programmable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

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