Open Access

ARTICLE

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

by S. V. Ratankumar^1,2, L. Koteswara Rao^1,*, M. Kiran Kumar³

1 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Aziz Nagar, Hyderabad, 500075, Telangana, India
2 Department of Electronics and Communication Engineering, RGM College of Engineering and Technology, Nandyal, 518501, Andhra Pradesh, India
3 Department of Electrical and Electronics Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, 522502, Andhra Pradesh, India

* Corresponding Author: L. Koteswara Rao. Email:

Computers, Materials & Continua 2022, 73(3), 5283-5298. https://doi.org/10.32604/cmc.2022.027975

Received 30 January 2022; Accepted 05 May 2022; Issue published 28 July 2022

Abstract

The design of a three-input logic circuit using carbon nanotube field effect transistors (CNTFETs) is presented. Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices, which is why this design is so popular, and it also reduces chip area, both of which are examples of circuit overheads. The proposed module we have investigated is a triple-logic-based one, based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values, as well as comparisons of the design working with various load capacitances. Comparing the proposed design with the existing design, the delay times was reduced from 66.32 to 16.41 ps, i.e., a 75.26% reduction. However, the power dissipation was not optimized, and increased by 1.44% compared to the existing adder. The number of transistors was also reduced, and the product of power and delay (P*D) achieved a value of 0.0498053 fJ. An improvement at 1 V was also achieved. A load capacitance (fF) was measured at different values, and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps, with a range of 61.06 ps. The power dissipations ranged from a minimum of 3.38 µW to a maximum of 6.49 µW. Based on these results, the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

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Keywords

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