Open Access iconOpen Access

ARTICLE

crossmark

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer

Sha Li1,2, Qiao Meng1,*, Irfan Tariq1, Xi Chen3

1 Institute of RF- & OE-ICs, Southeast University, Nanjing, 210096, China
2 Jiangsu Key Construction Laboratory of IoT Application Technology, Wuxi Taihu University, Wuxi, 214064, China
3 Polytechnic University of Madrid, Madrid, 28031, Spain

* Corresponding Author: Qiao Meng. Email: email

Computers, Materials & Continua 2022, 72(3), 6079-6090. https://doi.org/10.32604/cmc.2022.027404

Abstract

This article presents a high speed third-order continuous-time (CT) sigma-delta analog-to-digital converter (SDADC) based on voltage-controlled oscillator (VCO), featuring a digital programmable quantizer structure. To improve the overall performance, not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise. Due to the intrinsic first-order noise-shaping of the VCO quantizer, the proposed third-order SDADC can realize forth-order noise-shaping ideally. As a bright advantage, the proposed programmable VCO quantizer is digital-friendly, which can simplify the design process and improve anti-interference capability of the circuit. A 4-bit programmable VCO quantizer clocked at 2.5 GHz, which is proposed in a 40 nm complementary metal-oxide semiconductor (CMOS) technology, consists of an analog VCO circuit and a digital programmable quantizer, achieving 50.7 dB signal-to-noise ratio (SNR) and 26.9 dB signal-to-noise-and-distortion ration (SNDR) for a 19 MHz − 3.5 dBFS input signal in 78 MHz bandwidth (BW). The digital quantizer, which is programmed in the Verilog hardware description language (HDL), consists of two-stage D-flip-flop (DFF) based registers, XOR gates and an adder. The presented SDADC adopts the cascade of integrators with feed-forward summation (CIFF) structure with a third-order loop filter, operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.

Keywords


Cite This Article

S. Li, Q. Meng, I. Tariq and X. Chen, "A 78-mhz bw continuous-time sigma-delta adc with programmable vco quantizer," Computers, Materials & Continua, vol. 72, no.3, pp. 6079–6090, 2022. https://doi.org/10.32604/cmc.2022.027404



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • 1219

    View

  • 720

    Download

  • 0

    Like

Related articles

Share Link