Open Access

ARTICLE

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

Hojin Kang¹, Syed Asmat Ali Shah², HyungWon Kim^1,*

1 Department of Electronics Engineering, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, 28644, Korea
2 Department of Electrical and Computer Engineering, COMSATS University Islamabad, Abbottabad Campus, Abbottabad, 22060, Pakistan

* Corresponding Author: HyungWon Kim. Email:

Computers, Materials & Continua 2022, 72(1), 2127-2139. https://doi.org/10.32604/cmc.2022.025798

Received 05 December 2021; Accepted 24 January 2022; Issue published 24 February 2022

Abstract

This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes. The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor (CMOS) library using Cadence Virtuoso design tool. Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3% compared with conventional SAR ADC, compared with the SAR ADC with split capacitor, and compared with the resistor and capacitor (R&C) Hybrid SAR ADC. The ADC achieves an effective number of bits (ENOB) of bits and consumes at sampling rate of , offering an energy consumption of per conversion step. The proposed SAR ADC offers 95.5% reduction in chip core area compared to conventional architecture, while occupying an active area of .

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Keywords

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