Open Access

ARTICLE

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Rajkumar Sarma¹, Cherry Bhargava², Ketan Kotecha^3,*

1 Department of Electrical & Electronics Engineering, Faculty of Engineering & Technology, Jain (Deemed-to-be-University), Ramanagar, 562112, Karnataka, India
2 Symbiosis Institute of Technology, Symbiosis International (Deemed University), Lavale, Pune, 412115, India
3 Symbiosis Centre for Applied Artificial Intelligence, Symbiosis International (Deemed University), Lavale, Pune, 412115, India

* Corresponding Author: Ketan Kotecha. Email:

(This article belongs to the Special Issue: Soft Computing and Machine Learning for Predictive Data Analytics)

Computers, Materials & Continua 2022, 72(1), 481-495. https://doi.org/10.32604/cmc.2022.024516

Received 20 October 2021; Accepted 22 December 2021; Issue published 24 February 2022

Abstract

In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872)₁₀ to + (7.96872)₁₀. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as “block enabling” and “clock gating” are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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Keywords

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