Open Access

ARTICLE

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

by Arpit Jain¹, Rakesh Kumar Dwivedi¹, Hammam Alshazly^2,*, Adesh Kumar³, Sami Bourouis⁴, Manjit Kaur⁵

1 Faculty of Engineering & Computer Sciences, Teerthanker Mahaveer University, Moradabad, Uttar Pradesh, 244001, India
2 Faculty of Computers and Information, South Valley University, Qena, 83523, Egypt
3 Department of Electrical and Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India
4 Department of Information Technology, College of Computers and Information Technology, Taif University, Taif, 21944, Saudi Arabia
5 School of Engineering and Applied Sciences, Bennett University, Greater Noida, 201310, India

* Corresponding Author: Hammam Alshazly. Email:

(This article belongs to the Special Issue: Recent Advances in Metaheuristic Techniques and Their Real-World Applications)

Computers, Materials & Continua 2022, 71(2), 4085-4100. https://doi.org/10.32604/cmc.2022.023017

Received 25 August 2021; Accepted 01 November 2021; Issue published 07 December 2021

Abstract

The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

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