Open Access
ARTICLE
High Throughput Scheduling Algorithms for Input Queued Packet Switches
1 Department of IT, Dr. Sivanthi Aditanar College of Engineering, Tiruchendur, 628205, India
2 Department of CSE, Dr. Sivanthi Aditanar College of Engineering, Tiruchendur, 628205, India
3 School of CSE, Vellore Institute of Technology, Vellore, 632014, India
* Corresponding Author: R. Chithra Devi. Email: