This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

Internet of Things (IoTs) can connect many devices together to formulate a smart network, which can be used in smart home, intelligent transportation, smart grid, wise medical, smart agriculture and smart cities [

To improve the energy efficiency and resolution of SAR ADC, researches focused on digital-to-analog converter (DAC) switching scheme and comparator have been developed [

Comparator performance is another challenge in SAR ADC design, especially for high resolution ADC, where the noise performance is of great importance. For traditional voltage-domain comparator, every 1-bit resolution improvement in signal-to-noise ratio (SNR) requires four times power consumption of the comparator, which results in less energy-efficient. To improve the energy-efficiency, time-domain comparators are developed [

To further improve the overall power-efficiency, different window techniques for SAR ADC are proposed [

In this paper, a SAR ADC model with skipping window is proposed. Its key feature is the utilization of a time-domain comparator information to implement the skipping window technique to improve the energy efficiency. The rest of this paper is organized as follows. Section 2 describes the structure of the proposed SAR ADC. The analysis of the skipping window is given in Section 3. Simulation results are given in Section 4. Section 5 concludes this paper.

The proposed SAR ADC architecture with skipping-window is shown in

The proposed time-domain comparator is illustrated in

The noise root mean square (rms) level

where

_{cm}. Then the control logic changes the connections of the bottom plates in order to generate the window voltage _{win}. After the DAC settles, the comparator starts to work and the counter number _{win} under _{win} will be recorded. _{win} will be utilized to indicate whether the input voltage falls into the skipping window during the SAR conversion. A SAR conversion will start after the _{win} is set. After the sampling process, the SAR control logic set the current conversion cycle _{win}, the SAR control logic will perform the normal SAR conversion cycle by cycle; otherwise, the control logic will judge whether the current conversion cycle _{win}; if _{win}, the control logic sets _{win}, and perform the rest conversion cycles. Once _{win}, the control logic will perform the normal conversion.

_{win} = 64 LSBs. The most significant bit (MSB) cycle is denoted as phase 9, and the least significant bit (LSB) cycle is phase 0. _{win} at phase 6, where phase 6 corresponds to the window of 64 LSBs. Thus, no window is skipped for this case. In _{win} at phase 8, the next conversion cycle will skip to phase 5 directly, and two comparison cycles are saved. Thus, when the skipping window triggers, the conversion cycles will reduce, which in turn helps to improve the energy efficiency of the SAR ADC as well as the conversion speed and linearity.

The DAC switching scheme employed here is similar to that used in [_{cm}, which is represented by ‘1/2’ in _{win}. If |_{ip} _{in}| < _{win}, it means the input voltage is within the voltage window. Under this case, the skipping step is triggered. If _{ip} _{in}, the bottom plates of _{ip} _{in}, the switching procedure is just opposite to that of _{ip} _{in} as the branch B shows in _{ip} _{in}| > _{win}, the skipping procedure is not triggered, and normal conversion process is performed as branches C and D show. It should be noted that, whenever the input voltage is less than _{win} before phase 6, the skipping procedure will be triggered, which is different from the incremental algorithm in [

To prove the efficiency of the proposed skipping window technique when the input falls in the predefined window voltage _{win}, different window voltages are defined to verify the conversion cycle saving. During simulations, a 10-bit SAR ADC model is used.

As described in Section 2.2, a large voltage range of the full scale input can fall in the skipping window zone if _{win} is small. However, when _{win} is small, the first MSB cycles can be skipped is less, which results in less energy efficiency of DAC. In order to evaluate the effect of the skipping window size on the DAC switching energy, a 10-bit SAR ADC model with the merged capacitor switching (MCS) scheme in [

In SAR ADC, most of the power is consumed by three main building blocks, including comparator, DAC capacitor arrays and control logic. Since the DAC switching energy is not the same for different cycles during a conversion, the energy saving with different window size can be evaluated by supposing that each output code has the same probability, and the average DAC switching energy is denoted as _{DAC}. For simplicity, we assume that the power consumption for the comparator _{comp} and the control logic _{dig} do not change for each bit-cycle.

For a normal conversion cycle, the power consumption for the comparator and the control logic are _{win}, the cycles between

where

In order to evaluate the performance of the proposed skipping window technique, a 10-bit SAR ADC model is used. During simulations, the power consumption of the comparator and the control logic is assumed unchanged for each bit-cycle.

256 LSBs | 128 LSBs | 64 LSBs | 32 LSBs | 16 LSBs | 8 LSBs | 4 LSBs | 2 LSBs | |
---|---|---|---|---|---|---|---|---|

Bit-cycles saving (%) | 5 | 10 | 13.75 | 16.25 | 17.81 | 18.75 | 19.3 | |

DAC energy saving (%) | 28.2 | 34.8 | 25.9 | 17.5 | 11 | 6.7 | 3.9 | |

Overall power saving (%) | 11.96 | 18.64 | 19.145 | 17.717 | 16.425 | 15.52 | 14.89 |

A SAR ADC with skipping window is presented. The proposed comparator provides not only the polarity information of the input, but also the amount of the input difference, which is employed to indicate the window voltage. The window voltage can be easily adjusted by connecting different DAC capacitors to corresponding reference voltages. The impacts on the DAC switching power and the conversion cycles are analyzed. Simulation results show that the proposed skipping window can effectively improve the overall energy-efficiency of SAR ADC.

_{CM}