Open Access
ARTICLE
A Two-Dimension Time-Domain Comparator for Low Power SAR ADCs
Liangbo Xie1, *, Sheng Li1, Yan Ren1, Zhengwen Huang2
1 School of Communications and Information Engineering, Chongqing University of Posts and
Telecommunications, Chongqing, 400065, China.
2 Department of Electronic and Computer Engineering, Brunel University, Uxbridge, Middlesex, UB8 3PH, UK.
* Corresponding Author: Liangbo Xie. Email: .
Computers, Materials & Continua 2020, 65(2), 1519-1529. https://doi.org/10.32604/cmc.2020.011701
Received 25 May 2020; Accepted 16 June 2020; Issue published 20 August 2020
Abstract
This paper presents a two-dimension time-domain comparator suitable for low
power successive-approximation register (SAR) analog-to-digital converters (ADCs). The
proposed two-dimension time-domain comparator consists of a ring oscillator collapsebased comparator and a counter. The propagation delay of a voltage controlled ring
oscillator depends on the input. Thus, the comparator can automatically change the
comparison time according to its input difference, which can adjust the power consumption
of the comparator dynamically without any control logic. And a counter is utilized to count
the cycle needed to finish a comparison when the input difference is small. Thus, the
proposed comparator can not only provide the polarity of the input, but also the amount
information of the input, which helps to skip most of the SAR cycles when the initial input
is small. Thus, most energy can be saved when the initial input is small. The proposed timedomain comparator is designed in 0.18 μm CMOS technology. Simulation results
demonstrate that the comparator can not only save power consumption, but also give the
design flexibility, and the current is only nA level when the supply voltage is 0.6 V.
Keywords
Cite This Article
L. Xie, S. Li, Y. Ren and Z. Huang, "A two-dimension time-domain comparator for low power sar adcs,"
Computers, Materials & Continua, vol. 65, no.2, pp. 1519–1529, 2020. https://doi.org/10.32604/cmc.2020.011701