Open Access

ARTICLE

Numerical Simulation of Fatigue Crack Growth in Microelectronics Solder Joints

by K. Kaminishi¹, M. Iino², H. Bessho², M. Taneda³

1 Department of Mechanical Engineering, Yamaguchi University, 2557 Toki-wadai, Ube City, 755-8611, Japan
2 Department of Mechanical Engineering, Yamaguchi University, 2557 Toki-wadai, Ube City, 755-8611, Japan
3 Department of Mechanical Engineering, Fukuyama University, GakuenCho 1, Fukuyama City, 729-0292, Japan

Computer Modeling in Engineering & Sciences 2000, 1(1), 107-110. https://doi.org/10.3970/cmes.2000.001.107

Abstract

An FEA (finite element analysis) program employing a new scheme for crack growth analysis is developed and a prediction method for crack growth life is proposed. The FEA program consists of the subroutines for the automatic element re-generation using the Delaunay Triangulation technique, the element configuration in the near-tip region being provided by a super-element, elasto-inelastic stress analyses, prediction of crack extension path and calculation of fatigue life. The FEA results show that crack extension rate and path are controlled by a maximum opening stress range, Δσ_θmax, at a small radial distance of r = d, where d is chosen to be a grain diameter's distance, 3.5 μm, in solder material. The experimentally obtained crack extension rate is found to be related to Δσ_θmax in FEA as da/dN = β[Δσ_θmax - γ]^α, where α = 2.0, β = 4.5 × 10^-9 mm⁵/N² and γ = 98 M Pa are determined for all test conditions. The calculated values of crack extension life by the FEA using the above equation are in good agreement with the experimental ones and are independent of the joint types.

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Keywords

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